1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly relates to a semiconductor device including trench gate transistors (trench gate is also referred to as “recess channel”, see Japanese Patent Application Laid-open Nos. 2005-322880, 2006-173429, and 2006-261627) and a manufacturing method of the semiconductor device.
2. Description of Related Art
Generally, in a manufacturing method of a semiconductor device, fine patterns are formed by photolithography and dry etching.
FIGS. 26A and 26B show a configuration of memory cell transistors of an ordinary DRAM, where FIG. 26A is a schematic plan view and FIG. 26B is a schematic cross-sectional view taken along a line B-B of FIG. 26A.
As shown in FIGS. 26A and 26B, STI (Shallow Trench Isolation) regions 401 are formed in a semiconductor substrate 400 by photolithography and dry etching, thereby defining and dividing active regions 402. Gate electrodes 403 each having an upper surface covered with a cap insulating film 405 and a side surface covered with a sidewall insulating film 406 are provided to cross the active regions 402. Contact plugs 407 are formed on diffusion layers 404 provided on both sides of each gate electrode 403 so as to be connected to the diffusion layers 404, respectively. In the example shown in FIGS. 26A and 26B, the active regions 402 are formed to be sufficiently wide on both sides of the gate electrodes 403. Due to this, the diffusion layers 404 are also formed to be sufficiently large. This arrangement enables each contact plug 407 and the diffusion layer 404 corresponding to the contact plug 407 to be connected to each other by as much as a sufficient area, thus suppressing contact resistance to be low.
However, along with downscaling of semiconductor devices, it has been difficult to form fine patterns by photolithography and dry etching. For example, the following problems occur when the active regions surrounded by the STI regions in a region where memory cells are formed to have minimum working dimensions such as a memory cell region of a DRAM.
FIGS. 27A and 27B show a configuration of memory cell transistors when the distance between two adjacent active regions is narrower, where FIG. 27A is a schematic plan view and FIG. 27B is a schematic cross-sectional view taken along a line B-B of FIG. 27A. In FIGS. 27A and 27B, constituent elements identical to those in FIGS. 26A and 26B are denoted by like reference numerals and explanations thereof will be omitted.
In FIGS. 27A and 27B, the distance between two adjacent active regions 502 is made narrower, and thus photolithography and dry etching are not performed satisfactorily, so that an area of each of the active regions 502 defined and divided by STI regions 501 is reduced. This reduces areas of the diffusion layers 504. As indicated by a dotted line in FIG. 27A, a contact area by which one contact plug 407 contacts with the diffusion layer 504 corresponding to the contact plug 407 is considerably reduced. Accordingly, there occurs a problem that contact resistance considerably increases.
While problems of conventional techniques have been described while referring to a memory cell region of a DRAM by way of example, these problems similarly and possibly occur to peripheral regions of a DRAM and in formation of fine patterns in other semiconductor devices.